Disco: The Saw Every Chip on Earth Passes Through

1The most boring monopoly in semiconductors

After the billion-dollar lithography is done, every wafer meets a saw. Back-end processing - thinning wafers from ~775 microns down to sometimes under 50, dicing them into individual die by blade or laser, polishing the results - is the least romantic step in the industry and the most expensive place to fail, because a wafer scrapped here carries its full accumulated value.

Disco, which began in 1937 grinding abrasive wheels, owns roughly three-quarters of this equipment market by most industry accounts, with Tokyo Seimitsu (Accretech) holding most of the rest. A duopoly with a dominant head, in a step no chip skips.

2How the share compounds

The model is razor-and-blade: precision machines plus proprietary blades, wheels and consumables that wear by design. Eighty years of abrasives know-how sits in the consumable, and Disco's application labs co-develop cutting and grinding recipes with customers for each new package - know-how that transfers to the next machine purchase and nowhere else.

As with chucks and films earlier in this series, the moat is accumulated process intimacy. Nobody re-qualifies the saw that already works, on a step where failure destroys finished value.

3HBM made grinding glamorous

High-bandwidth memory - the stacked DRAM on every serious AI accelerator - requires wafers thinned to roughly 30 microns so eight or twelve of them can be stacked and bonded. Ultra-thin grinding at yield is exactly Disco's franchise, and every HBM stack multiplies demand for it. Micron (MU), SK Hynix and Samsung capex flows through this layer on its way to Nvidia.

The same is true of advanced packaging generally: chiplets, wafer-on-wafer bonding and interposer assembly all begin with Disco-class thinning and end with Disco-class singulation. The buildout the market prices as CoWoS is, one layer down, a grinder order book.

4Who feels a Disco problem

The OSATs - Amkor (AMKR), ASE - run floors of these machines; memory makers and foundries (MU, TSM) run more. A serious disruption at Disco's Japanese plants would surface in earnings calls across the packaging complex within two quarters, attributed to 'back-end capacity' by companies that never say the vendor's name.

Japan-concentrated production puts this layer, like the others in this series, inside the seismic geography our world-risk board tracks - and it is the strongest single argument for extending that board a tier below the fabs.

5The investable surface, honestly

Disco trades in Tokyo (6146) with an OTC ADR (DSCSY) - a direct, liquid-in-Tokyo expression of the thesis, unusual for this series. The subtler use is as an indicator: Disco's orders and consumable sales are a leading read on advanced-packaging volume - ahead of what AMKR, MU or TSM back-end capex discloses.

As throughout: this is a map of a narrow, load-bearing layer. Thin is not the same as cheap, and no part of this note is a recommendation.

Sources and method

Compiled from public filings, company disclosures and trade press, cross-checked against our desks where they overlap. Supply shares in private industrial chains are estimates, are labelled as estimates, and the ones we could not verify are listed under what we do not know rather than asserted. The lines below are the factual spine.

• Disco holds roughly 70-80% of the dicer/grinder market by trade consensus, with Accretech the main alternative
• HBM stacking requires wafers thinned to ~30 microns (process literature)
• The business model pairs machines with proprietary consumable blades (company disclosures)

Underlying sources

• Disco Corporation disclosures and the company's kiru-kezuru-migaku segment reporting
• Trade press on back-end equipment share
• HBM process literature - wafer thinning requirements
• Parallax bottlenecks board - advanced packaging layer

Written by Parallax Research's research writer on 2026-07-29 and reviewed against the dossier it was given. Figures are as of that date and are not updated in place. Our scoring model's out-of-sample AUC is published in the whitepaper; nothing here is a forecast.